1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device having a sense amplifier.
2. Description of the Related Art
Basic operations in a semiconductor memory device such as a DRAM(Dynamic Random Access Memory), an SRAM(Static Random Access Memory), or a flash memory, include reading and writing data. There are usually minor differences among the memory types for the write operation, but there is little difference in the read operation. The read operation in a typical semiconductor memory device is controlled by a read enable signal that is applied by a switch to a corresponding memory cell or data read path, which provides an indication of a data read operation. A memory cell is enabled by electrically connecting a bit line and a word line to the memory cell. A word line is a line that is connected to a gate of a memory cell transistor, and a bit line is a line that is connected to a source or drain of the cell transistor. Thus, the read operation for a specific memory cell in a memory cell array is obtained after enabling the corresponding word line and bit line.
A flash memory reads data by sensing current, which is different from a DRAM. A current sense amplifier capable of sensing and amplifying is used to read data in the flash memory.
A current mirror is one example of a current sense amplifier. A current mirror has a stable operation, which results from a high noise immunity and a low operating voltage. But it has a shortcoming, namely a relatively high current consumption. Furthermore, another shortcoming is its long sensing times. There have been prior efforts to reduce the current consumption and the sensing time of the data.
The shortcomings of the conventional current mirror type sense amplifier were partially improved by the disclosure of U.S. Pat. No. 6,504,761, titled ‘Non-volatile semiconductor memory device improved sense amplification configuration’. This prior art is shown in FIG. 1.
As shown in FIG. 1, a non-volatile memory cell MC is connected to a sense amplifier unit 10 through a column selection transistor M5. The sense amplifier unit 10 includes an NMOS transistor M2, an inverter I1, PMOS transistors M1, M3, M6′ and an NMOS diode M4.
The inverter I1 inverts a signal of a bit line BL. The NMOS transistor M2 is connected between a node N1 and the bit line BL, and has its gate receiving an output of the inverter I1. The PMOS transistor M1 is connected between a power source Vcc and the node N1, and has its gate connected to the node N1. The PMOS transistor M3 is connected between the power source Vcc and an output node N2, and has its gate connected to the node N1. The PMOS transistor M1 and the PMOS transistor M3 have a configuration of a current mirror. A transistor M6′ is connected between the power source Vcc and the node N1, and is turned on or off by a control signal PC. The NMOS diode M4 is connected between the node N2 and a ground node. A sensing current flowing through the PMOS transistor M3 is converted to a voltage by the NMOS diode M4.
When a word line WL is selected and the column selection transistor M5 is turned on, a current of the memory cell MC is detected by the sense amplifier unit 10, and a sensing current is converted to a voltage. Sensed data (voltage) is output from the node N2. Thus, the data value of the memory cell MC is determined.
To precharge the bit line before a sense operation, the control signal PC is set low, thus turning on the PMOS transistor M6′, which precharges the node N1 to the level of the power source Vcc. When the PMOS transistor M6′ is turned on and the precharge operation is completed, the PMOS transistor M3 turns off. Thus, the current does not flow through the PMOS transistor M3 and the NMOS transistor M4, reducing current consumption during the precharging operation.
Although this sense amplifier reduces the consumption of current, it does not reduce the sensing time for sensing data. The sense amplifier of a conventional single ended system utilizes a current on the sensing node via a current mirror, and not a current flowing in a main cell and a reference cell. That is, this conventional sense amplifier has a configuration for sensing a voltage shifted by a current difference.
The time it takes to sense data stored in a memory cell depends upon how quickly the sensed current reaches a stabilized state. For example, if the cell transistor is in an on-state, then data sensing is valid when the data sensing current is above a determined reference current. That is, when the sensed current begins to be in a steady state, the current sensed for an on-cell is greater than the reference current. Conversely, a current sensed for an off-cell is less than the reference current. A precharge time is defined as the time it takes for the reference current flowing in the reference cell and the cell current flowing in the memory cell to become equal to a precharge current.
In order to sense the memory cell in the sense amplifier, the precharge is started by supplying current to the data line through a PMOS load. The bit line is charged by the supply of the precharge current, thus a precharge voltage increases and a current flows to the sensing memory cell. At this time, in sensing a cell having a high threshold voltage Vt, the current flowing in the cell is very small, and so the precharge time is very long.
FIG. 2 is a graph illustrating a precharge time for on-cell and off-cell. In FIG. 2, the horizontal axis represents time and the vertical axis represents current.
As shown in FIG. 2, there is a problem that the precharge time t2 for the off cell is longer than a precharge time t1 for the on cell. That is, the precharge time t2 for the off cell becomes the total precharged time of the sense amplifier. Reducing this precharge time can reduce the data sensing time.
The precharge time can be reduced by decreasing the current consumption during the sensing operation and simultaneously enabling a sensed current to reach a steady state in a shorter time. Thereby a semiconductor memory device capable of increasing data sensing speed is desired.